Semiconductor devices are formed with circuit components on and/or in a substrate layer. The substrate layer may, for example, be a bulk semiconductor substrate or silicon on insulator substrate (SOI). The fabrication of the circuits is referred in the art as a front end of line (FEOL) process. After the FEOL process is completed, the fabrication of the device is finished by forming a network of signal and power paths to connect to the circuit components. This is referred in the art as a back end of line (BEOL) line process.
Routing of the paths in the BEOL process requires the formation of multiple levels (or layers) of metallization over the substrate layer that includes the circuits formed during the FEOL process. The metallization includes metal vias which extend perpendicular to a top surface of the substrate layer and metal lines which extend parallel to the top surface of the substrate layer. It is common to use copper (Cu) as the metal material for the vias and lines, although it is known in the art to use other metal materials as well. The metallization includes an insulating dielectric material at leach level, with the vias and lines being surrounded by the insulating dielectric material.
As semiconductor devices become smaller and more complex, there is a corresponding increase in the complexity of the BEOL metallization including a requirement for increasingly smaller dimensioned metallization structures. This effect is even more pronounced with respect to vias making connections between levels. It is important in forming the via to maintain the desired via dimensions. This is especially critical at the point where the via makes contact with a metal line of an underlying metallization level.